Lane Departure Warning (LDW) systems require high-performance digital image processing as well as low-cost platforms appropriate for the typical volumes of the automotive market. Field Programmable Gate Array (FPGA) devices are capable of meeting these two contrasting requirements. Nevertheless, algorithm and system designers new to FPGA technology may assume incorrectly that the only way to program an FPGA is with a Hardware Description Language (HDL), but in fact, this is no longer the case. In this paper, we present a RANSAC algorithm for Lane Model Fitting within a LDW FPGA-based demonstrator. The adoption of Model-Based Design methodology, applying the Simulink modelling tool and the Xilinx System Generator for DSP synthesis tool, provided us an efficient and straightforward method for transitioning from a purely Simulink algorithmic model to a real time FPGA hardware implementation, without any need of HDL coding. Using this methodology we achieve an excellent overall performance in terms of silicon area occupation, high image quality and short development time.
Automotive driver assistance system development: Simplifying the transition from simulink to FPGA
2009
11 Seiten, 11 Bilder, 1 Tabelle, 8 Quellen
(nicht paginiert)
Conference paper
English