Over the past decade, the amount of processing utilized in spacecraft has increased. From below 1 MIP in the 1980s to single digit MIPS in the early 1990s to 10s of MIPS by the end of the twentieth century to hundreds of MIPS today, the amount of processing is in an upward trend paralleling though lagging the commercial and military embedded processing markets. This has allowed processing to move from simple control and data handling (C&DH) into payloads and other data processing intensive areas. Along with this memory capacities have increased to provide storage for programs and data. In the 1990s architectures to support processing and C&DH systems utilized bussed interconnects such as MIL-STD- 1553B and Peripheral Component Interconnect (PCI) for most communications between processing elements. Though these interfaces have been subject of improvements in speed and bandwidth, needs for data processing have increased at a rate that has overwhelmed the ability of these busses to provide all the desired data interconnects. During the 1990s, medium complexity glue logic surrounding application specific integrated circuits (ASIC) were the dominant form of realizing electronics in space. In this decade, fuse-based field programmable gate arrays (FPGA) with their radiation hardness and shorter development times, have been utilized much more in creating new space electronics. Memory-based FPGAs have begun to be used as developers around the world work on ways to mitigate radiation effects in order to take advantage of their higher performance and density and make possible spaceborne re configurable processing systems. BAE Systems has been at the forefront of processing solutions for space since the late 1980s with the GVSC, RAD6000(TM) and RAD750(TM) processors and their insertion into boards, boxes, payloads and hundreds of spacecraft over the past 15 years. Utilizing that experience, BAE Systems continues to push the envelope for high performance space-based processing systems. This paper discusses enhancements to the RAD750 family including the recently tested higher speed processor chips, the next generation bridge ASIC, the L2 Cache chip and the results of these tested improvements in processor system performance. It also describes how the SpaceWire ASIC developed for NASA Goddard increases the architectural choices available for interconnecting systems today and how our SERDES test chips that will enable higher performance interconnects and standards to be utilized for data movement in future systems. Finally, the paper describes the recent development of synergistic and high density reconfigurable processing elements including the Universal FPGA Support Device and a test board for exploring plug and play, SpaceWire and reconfigurable processor mitigation techniques. Taken together, these snapshot BAE's continued march of higher processing capability for spacecraft systems and payloads.


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    Title :

    Higher performance BAE systems processors and interconnects enabling spacecraft applications


    Contributors:
    Marshall, J.R. (author) / Wood, N. (author) / Milliser, M. (author) / Ferguson, R. (author) / Maher, E. (author)


    Publication date :

    2009


    Size :

    10 Seiten, 18 Quellen




    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




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