Of the many faulty SpaceWire implementations the authors have seen and analysed, most were due to the asynchronous interfaces. Unfortunately, asynchronous design is poorly supported by silicon design tools and simulation is particularly difficult. Asynchronous errors have been seen in practice even after extensive simulations detected no problems. The authors present an alternative design strategy that is fully synchronous and, as a result, can be implemented in FPGA (and ASIC) with no more constraint than specifying the (single) system clock frequency. Design tools are thus not limited in their ability to place user logic and hence are able to fully utilize the silicon. 4Links has built a large number of SpaceWire interfaces with this strategy and all have proved both simple to design and extremely robust in operation at speeds up to 500Mb/s. The authors begin by reviewing the commonly used asynchronous design technique, showing where difficulties arise, and proceed to describe the alternative, fully synchronous, approach that has proved to be easy to implement and robust in operation.


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    Title :

    Spacewire on FPGA - Challenges and solutions


    Additional title:

    Spacewire auf FPGA - Herausforderungen und Lösungen


    Contributors:


    Publication date :

    2008


    Size :

    4 Seiten, 5 Bilder, 1 Tabelle, 2 Quellen




    Type of media :

    Conference paper


    Type of material :

    Storage medium


    Language :

    English




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