As a step towards a real-time signal aperture radar (SAR) correlator, custom very large scale integration (VLSI) architectures are developed. Considering the extremely short word length of the data, we derive three architectures with massive parallelism in bit space. Unlike frequency methods, no. degradation is introduced during convolution. Optimized for time and space, they are highly suited to VLSI implementation, and a small architecture with 80 taps operating at 10 MHz has been built using an FPGA.


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    Title :

    VLSI architecture for SAR data compression


    Contributors:
    Jeong, H. (author) / Park, J.H. (author) / Ryu, H.Y. (author) / Kwon, J.B. (author) / Oh, Y. (author)


    Publication date :

    2002


    Size :

    14 Seiten, 19 Quellen




    Type of media :

    Article (Journal)


    Type of material :

    Print


    Language :

    English




    VLSI architecture for SAR data compression

    Jeong, H. / Park, J.H. / Ryu, H.Y. et al. | IEEE | 2002




    Parallel VLSI Architecture

    Truong, T. K. / Reed, I. / Yeh, C. et al. | NTRS | 1985