Synthetic scene generation systems require huge computational resources to operate on potentially large data sets of information and to interface to advanced sensor technology via current scene projectors. Nallatech Ltd. has been focused in the area of low latency hardware and algorithm development for many years. In collaboration with Matra British Aerospace Dynamics UK, minimum latency systems have already been developed offering latency of only several video lines in 3D target scene generation systems. The rapid progression of FPGAs towards 1 million gate devices together with the ever increasing performance of today's DSPs have allowed Nallatech to formulate an architecture that is particularly suited to HWIL systems. This paper is presented in two sections: Nallatech discusses these new architectures and shows the specific performance advantages for HWIL applications of these concepts over conventional processor architectures. This is aimed at supporting IR seeker and tracker HWIL systems. MBDUK is proceeding on upgrading existing target scene generation facilities to this latest architecture. A description of the target, radiance and atmospheric modeling complexity is presented along with a novel method of exhaust plume and flare modeling using the particle method. Simulations of several thousand particles are demonstrated providing realistic signatures in terms of spatial dynamics and IR radiance.
Ultra high performance image processing architectures for hardware-in-the-loop testing
1999
12 Seiten, 4 Quellen
Conference paper
English
Improving Hardware-In-The-Loop Testing
AIAA | 2005
|Survivability Test of High-performance Image Processing Hardware
British Library Online Contents | 1996
|Survivability Test of High-Performance Image Processing Hardware
British Library Conference Proceedings | 1996
|Hardware-in-the-Loop Testing in Racing Applications
SAE Technical Papers | 2004
|Hardware-in-the-Loop Testing for Optimizing Inverter Performance in Electric Vehicles
SAE Technical Papers | 2023
|