A fault tolerant computer architecture that rigorously meets all the known requirements for tolerating random hardware faults and its hardware and software implementation have been described. This architecture is based on a sound theoretical foundation. The fault containment zones are rigorously defined and implemented to tolerate any arbitrary failure mode including Byzantine failures. The computational core is designed to contain output errors. From a users' viewpoint, the fault tolerance and redundancy management are totally invisible. The architecture maintains a high fidelity to the simplex programming model. Software developed on a signle string computer can be ported to the fault tolerant version of the computer with little or no modification. The redundancy management itself is highly efficient and consumes no more than five percent of the microprocessor throughput. We are currently fabricating a VLSI version of the fault tolerant processor that has the characteristics just summarized. It is being designed around a 20 MHz version of the Motorola 68020 32-bit microprocessor and includes the Motorola 68881 Floating Point Co-processor which should significantly improve its throughput. In addition, the testability, maintainability and reliability of the FTP are being improved. The use of higher density devices, including Configurable Gate Arrays, will reduce the number of components used in the FTP.


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    Title :

    A fault tolerant processor to meet rigorous failure requirements


    Additional title:

    Ein fehlertoleranter Prozessor zur Erfuellung der strengen Anforderungen an die Zuverlaessigkeit


    Contributors:
    Lala, J.H. (author) / Alger, L.S. (author) / Gauthier, R.J. (author)


    Publication date :

    1986


    Size :

    8 Seiten, 6 Bilder, 8 Quellen


    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




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