This paper presents a practical model and procedures for analyzing combined hardware and software reliability of embedded computer systems. The emphasis is on combined hardware and software reliability qualification testing. The model was developed and applied to measurement and prediction of reliability performance and to contractual definition of combined hardware-software warranty provisions for weapons and communications systems. The method of hardware-software reliability analysis and test exhibits the following features: A Bayes prior for the probability that the software contains errors which is updated as test data is accumulated. The combination of hardware and software failure data yields a total system reliability estimate after each test. A decision rule treatment of test design for continuation or termination of testing based on specified consumer and producer risks and observed test results. The identification of each system malfunction as one of three types: (1) hardware related, (2) software related, or (3) unknown or ambiguous source related. Bayes inference procedures are used for reliability estimation and test design. The Bayes model provides a means for combining hardware and software reliability estimates to obtain total system reliability. The model allows software redesign and repair after software related system malfunctions are observed in a test phase. This feature is useful for maintaining specified risk when repairs are allowed at the end of successive test phases. The classical analysis procedure and test design does not allow this feature in any simple way.
System hardware and software reliability analysis
System-Hardware- und Software-Zuverlaessigkeitsanalyse
1983
4 Seiten, 21 Quellen
Conference paper
English
Developing Integrated Hardware-Software Reliability Models: Difficulties and Issues
British Library Conference Proceedings | 1995
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|Tema Archive | 1983
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