Compared with the SC decoder, BP decoder provides a higher throughput and lower decoding latency for its inherent parallel nature. However, the functional units of existing BP decoders are not fully utilized. In this paper, we propose a new update scheduling scheme and hardware optimization design to improve the hardware efficiency of BP decoder. First, a pipelined decoder architecture is proposed to reduce the consumption of functional units. Then, a new update scheduling scheme is proposed, when updating the messages, both new-value and old-value approaches are used to improve the utilization of functional units and reduce the decoding latency. The analysis and synthesis results have shown that, compared with the existing methods, the proposed decoder suffers from a slight the decoding performance degradation, but the utilization rate of basic computational blocks (BCB) can be increased to 50.58%. The storage resource dissipation can be reduced by 20.1%–34.09%.
Pipelined BP Polar Decoder with a Novel Updated Scheme
Lect.Notes Social.Inform.
International Conference on Wireless and Satellite Systems ; 2020 ; Nanjing, China September 17, 2020 - September 18, 2020
2021-02-28
12 pages
Article/Chapter (Book)
Electronic Resource
English
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