A new processor architecture intended to be integrated with a CMOS image sensor is presented. This association allows to design an intelligent camera that can perform on-chip image processing tasks. The processor is based on a VLIW architecture with a reduced instruction bus, able to execute multiple instructions in a parallel without any loss of performance. In addition, no more instruction cache is required, decreasing in this way the hardware complexity.
VLIW processor architecture adapted to FPAs
Advanced Focal Plane Arrays and Electronic Cameras II ; 1998 ; Zurich,Switzerland
Proc. SPIE ; 3410
1998-09-07
Conference paper
Electronic Resource
English
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