A new processor architecture intended to be integrated with a CMOS image sensor is presented. This association allows to design an intelligent camera that can perform on-chip image processing tasks. The processor is based on a VLIW architecture with a reduced instruction bus, able to execute multiple instructions in a parallel without any loss of performance. In addition, no more instruction cache is required, decreasing in this way the hardware complexity.


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    Title :

    VLIW processor architecture adapted to FPAs


    Contributors:

    Conference:

    Advanced Focal Plane Arrays and Electronic Cameras II ; 1998 ; Zurich,Switzerland


    Published in:

    Publication date :

    1998-09-07





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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