Given the fact that multiplex bus architectures are gaining acceptance, the need arises for hardware capable of implementing the desired structure Off-the-shelf technology exists that can be utilized for the design and development of J1850 compatible nodes A systems engineering approach to the design of a J1850 compatible node is taken A genenc model of a network node is defined and the design of a simple node is described The results of a market survey of available hardware and design tools are presented. This information is then used to develop several design approaches which are described and evaluated.


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    Title :

    J1850 Compatible Node Development


    Additional title:

    Sae Technical Papers


    Contributors:

    Conference:

    International Congress & Exposition ; 1996



    Publication date :

    1996-02-01




    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




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