Coder/decoder constructed on single integrated-circuit chip. Handles data in variety of formats at rates up to 300 Mbps, correcting up to 3 errors per data block of 256 to 512 bits. Helps reduce cost of transmitting data. Useful in many high-data-rate, bandwidth-limited communication systems such as; personal communication networks, cellular telephone networks, satellite communication systems, high-speed computing networks, broadcasting, and high-reliability data-communication links.
Triple-Error-Correcting Codec ASIC
NASA Tech Briefs ; 18 , 6
1994-06-01
Miscellaneous
No indication
English
Triple-Error-Correcting Codec ASIC
Online Contents | 1994
APPARATUS FOR CORRECTING SIGHT ERROR AND METHOD FOR CORRECTING SIGHT ERROR USING THE SAME
European Patent Office | 2017
|European Patent Office | 2019
|ASIC Physical Layout for the HCD ASIC
Online Contents | 1998