Coder/decoder constructed on single integrated-circuit chip. Handles data in variety of formats at rates up to 300 Mbps, correcting up to 3 errors per data block of 256 to 512 bits. Helps reduce cost of transmitting data. Useful in many high-data-rate, bandwidth-limited communication systems such as; personal communication networks, cellular telephone networks, satellite communication systems, high-speed computing networks, broadcasting, and high-reliability data-communication links.


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    Title :

    Triple-Error-Correcting Codec ASIC


    Contributors:

    Published in:

    Publication date :

    1994-06-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English





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