Integrated circuit called timing sampler used to measure delays in complementary metal oxide/silicon logic gates. Circuit chip contains chains of inverters and metal traces having minimum parasitic delays (delay chains), circuits to compare pulse timings, and output multiplexer. Timing sampler enables delay measurements for both positive and negative logic-level transitions by use of variety of circuit geometries representing tentative practical designs.
Timing Sampler For Delay Measurements
NASA Tech Briefs ; 13 , 3
1989-03-01
Miscellaneous
No indication
English
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