Scheme devised for asynchronous-message communication system for Mark III hypercube concurrent-processor network. Network consists of up to 1,024 processing elements connected electrically as though were at corners of 10-dimensional cube. Each node contains two Motorola 68020 processors along with Motorola 68881 floating-point processor utilizing up to 4 megabytes of shared dynamic random-access memory. Scheme intended to support applications requiring passage of both polled or solicited and unsolicited messages.


    Access

    Access via TIB

    Check availability in my library


    Export, share and cite



    Title :

    Asynchronous Communication Scheme For Hypercube Computer


    Contributors:

    Published in:

    Publication date :

    1988-09-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




    Hyperswitch Network For Hypercube Computer

    Chow, Edward / Madan, Herbert / Peterson, John | NTRS | 1989


    Hypercube-Computer Analysis Of Electromagnetic Scattering

    Patterson, J. E. / Liewer, P. C. / Calalo, R. H. et al. | NTRS | 1990


    Optimal Repetition Scheme for Repeated Latin Hypercube Sampling

    Beachkofski, Brian / Grandhi, Ramana | AIAA | 2002


    Image-Processing Software For A Hypercube Computer

    Lee, Meemong / Mazer, Alan S. / Groom, Steven L. et al. | NTRS | 1992


    Electrostatic Particle-In-Cell Code For Hypercube Computer

    Ferraro, Robert D. / Liewer, Paulette C. / Decyk, Viktor K. | NTRS | 1992