Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.


    Access

    Access via TIB

    Check availability in my library


    Export, share and cite



    Title :

    Addressable Inverter Matrix Tests Integrated-Circuit Wafer


    Contributors:

    Published in:

    Publication date :

    1988-02-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




    Addressable-Matrix Integrated-Circuit Test Structure

    Sayah, Hoshyar R. / Buehler, Martin G. | NTRS | 1991


    Decomposition method for matrix-addressable microlaser arrays

    Nahata, H. R. / Murdocca, M. | British Library Conference Proceedings | 1995


    Performance evaluation of an addressable integrated ordnance system

    Boucher, Craig / Novotney, David | AIAA | 2001


    ThH1 64x64 Matrix-Addressable Arrays of GaN-based MicroLEDs

    IEEE | British Library Conference Proceedings | 2002


    Data transmission circuit, integrated inverter and automobile

    GAO YUAN / ZHAO PINGHUA | European Patent Office | 2021

    Free access