Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.


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    Title :

    Multiplier Architecture for Coding Circuits


    Contributors:
    Wang, C. C. (author) / Truong, T. K. (author) / Shao, H. M. (author) / Deutsch, L. J. (author)

    Published in:

    Publication date :

    1986-03-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




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