Shift register time-shared in proposed error-correcting code for tape-storage systems. Error-correcting code logic for blocks of 256-bit data words implemented by 14-stage-time-shared shift register, two 4,096bit RAM's and logic gates. Encoding and decoding logic implement generator polynomial that defines error-correcting code, and error correction based on algorithm also implemented by logic.
Encoding Scheme Reduces Hardware Requirements
NASA Tech Briefs ; 9 , 1
1985-06-01
Miscellaneous
No indication
English
Reuse of Requirements Reduces Time to Market
Tema Archive | 2010
|Seat Belt Hardware Performance Requirements
SAE Technical Papers | 2013
SEAT BELT HARDWARE PERFORMANCE REQUIREMENTS
SAE Technical Papers | 1995
SEAT BELT HARDWARE PERFORMANCE REQUIREMENTS
SAE Technical Papers | 1973
Seat Belt Hardware Performance Requirements
SAE Technical Papers | 2022