Shift register time-shared in proposed error-correcting code for tape-storage systems. Error-correcting code logic for blocks of 256-bit data words implemented by 14-stage-time-shared shift register, two 4,096bit RAM's and logic gates. Encoding and decoding logic implement generator polynomial that defines error-correcting code, and error correction based on algorithm also implemented by logic.


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    Title :

    Encoding Scheme Reduces Hardware Requirements


    Contributors:

    Published in:

    Publication date :

    1985-06-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




    Reuse of Requirements Reduces Time to Market

    Goldin, L. / Matalon-Beck, M. / Lapid-Maoz, J. | Tema Archive | 2010