This research presents an eleven-level multilevel inverter with decreased switching count and voltage stress. There are only 7 switches in the architecture, including 1 bidirectional switch and 2 capacitors. The inverter circuit is given a gate pulse using a straightforward nearest level control (NLC), which is a fundamental switching frequency-based approach. To demonstrate the advantages of the presented topology, a comparison with recent topologies in terms of switches, diodes, sources, and capacitors employed in numbers is made. According to the IEEE 519–2014 standard, the total harmonic distortion (THD) is 8.6%, which is almost within acceptable bounds. Eventually, using the software PLECS and MATLAB (SIMULINK), the recommended architecture has been operationally and functionally simulated. Its experimental validation is also being done on the setup for various loading circumstances.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Asymmetrical Eleven-Level Multilevel Inverter with Low Switching Count and Voltage Stress


    Contributors:


    Publication date :

    2023-08-09


    Size :

    2375785 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English




    An Asymmetrical Multilevel Inverter in Photovoltaic (PV) Application

    Yusop, Nur Iffah Amirah / Azli, Naziha Ahmad / Nordin, Norjulia Mohamad | TIBKAT | 2019


    An Asymmetrical Multilevel Inverter in Photovoltaic (PV) Application

    Yusop, Nur Iffah Amirah / Azli, Naziha Ahmad / Nordin, Norjulia Mohamad | Springer Verlag | 2019


    Cascade multilevel inverter based topology with reduced switch count

    Gupta, Hemant / Yadav, Arvind / Maurya, Sanjay | IEEE | 2020


    Asymmetrical Three-Phase Multilevel Inverter for Grid-Integrated PLL-Less System

    Kumar, Rohit / Chaudhari, Madhuri A. / Chaturvedi, Pradyumn et al. | IEEE | 2023