We propose a parallel architectural scheme that allows the transmission of data in a truly parallel format at OC-192 and higher rates. The parallel signals consist of clock, frame synchronization pulse and byte wide data bits. The clock signal is transported by using the least dispersed wavelength, /spl lambda//sub 0/, like any other data signal. Therefore, simultaneous transmission of clock with data eliminates the need for clock recovery circuitry and special encoding of data using scramblers. The synchronization pulse and the byte wide data bits are transported over wavelengths /spl lambda//sub 1/.../spl lambda//sub n/ which are adjacent to /spl lambda//sub 0/. The synchronization pulse is used in acquiring and maintaining frame sync. The simultaneous byte wide data, clock and sync. pulse transportation besides lowering the operating frequency of the electronics from 10 Gb/s to 1.25 Gb/s also eliminates the need for byte alignment.
Parallel architectural scheme for transporting clock, data and synchronization for OC-192 using WDM
Proceedings of LEOS'94 ; 1 ; 205-206 vol.1
1994-01-01
171295 byte
Conference paper
Electronic Resource
English
British Library Conference Proceedings | 1994
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