Real-time signal processing for a 16-channel phased array radar, including space-time adaptive processing (STAP) algorithms, has been implemented using a 29-node ruggedized version of an Intel Paragon. Techniques employed to efficiently implement each step of the signal processing are discussed. An overall throughput of 3.15 GFLOPS and processing efficiency of 48% has been achieved, indicating that embedded high performance computers can deliver a significant percentage of their advertised peak throughput under real system constraints.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Real-Time STAP demonstration on an embedded high performance computer


    Contributors:


    Publication date :

    1998-03-01


    Size :

    870373 byte




    Type of media :

    Article (Journal)


    Type of material :

    Electronic Resource


    Language :

    English



    Real-Time STAP Demonstration

    Linderman | Online Contents | 1998


    Stap voor stap meer zitplaatsen

    Kreibich, Rolf; Nolte, Roland | IuD Bahn | 2000


    OV-chipkaart komt stap voor stap dichterbij

    NS N.V. Nederlandse Spoorwegen Postfach P.O. Box 2025 NL - 3500 HA Utrecht | IuD Bahn | 2005


    Reduced-rank STAP performance analysis

    Peckham, C.D. / Haimovich, A.M. / Ayoub, T.F. et al. | IEEE | 2000


    Reduced-Rank STAP Performance Analysis

    Peckham, C.D. | Online Contents | 2000