The enclosed layout transistor is an alternative to reduce the radiation sensitivity of CMOS devices by avoiding thick field oxide paths between source and drain terminals. This prevents the increase of leakage current of devices working under radiation. The commonly adopted square geometry of this design brings asymmetry between source and drain, modifying characteristics such as output conductance and capacitance, if compared to a traditional layout. Therefore, considering analog designs, this may complicate the process of mapping a nonhardened design onto a radiation tolerant version, even if the aspect ratios ($W/L$) of the transistors are designed to be the same. In this article, we propose a pseudosymmetric version of enclosed layout devices in order to better approximate its electrical characteristics to the conventional layout style. This way, no significant modification on simulation and design validation flow is necessary. The devices were fabricated in a 130 nm process, being then characterized and compared with regular (nonsymmetric) ELTs as well as to conventional (two-edge) layout transistors. Results show a good agreement between the tested parameters of the pseudosymmetric ELTs and the correspondent two-edge devices.
Pseudosymmetric Enclosed Layout Transistors for Radiation Hardened Analog Applications
IEEE Transactions on Aerospace and Electronic Systems ; 59 , 2 ; 2072-2076
2023-04-01
1155803 byte
Article (Journal)
Electronic Resource
English
British Library Conference Proceedings | 1994
|Radiation hardened memories for space applications
IEEE | 2001
|7.0602 RADAR - Reconfigurable Analog and Digital Array for Radiation-Hardened Circuits
British Library Conference Proceedings | 2004
|