This work describes a 0.5u m CMOS implementation of a Folded Cascode OTA designed for minimum Input Referred Noise for non-implantable EEG SoC arrays. It is also described a small area PID feedback network using a high resistive pMOS pseudo-resistor and small integration capacitances for programmable gain control throughout parasitic insensitive nMOS switches. Simulation results show that it achieves about 2.2u Vrms of input referred noise for 6u A of total current at +-1.8 V supply voltage. The circuit provides a NEF of 4.55 within a 1.96 kHz bandwidth and midband gain of 40.22 dB.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Low Power Low Noise Neural Amplifier with Adjustable Gain


    Contributors:


    Publication date :

    2012-11-01


    Size :

    599007 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    Monolithic Adjustable Gain-Clamped Semiconductor Optical Amplifier

    Akbar, J. / Odedina, O.A. / Michie, C. et al. | British Library Online Contents | 2013


    An Adjustable Gain-Clamped Semiconductor Optical Amplifier (AGC-SOA)

    Michie, C. / Kelly, A. E. / Armstrong, I. et al. | British Library Online Contents | 2007