This work describes a 0.5u m CMOS implementation of a Folded Cascode OTA designed for minimum Input Referred Noise for non-implantable EEG SoC arrays. It is also described a small area PID feedback network using a high resistive pMOS pseudo-resistor and small integration capacitances for programmable gain control throughout parasitic insensitive nMOS switches. Simulation results show that it achieves about 2.2u Vrms of input referred noise for 6u A of total current at +-1.8 V supply voltage. The circuit provides a NEF of 4.55 within a 1.96 kHz bandwidth and midband gain of 40.22 dB.
Low Power Low Noise Neural Amplifier with Adjustable Gain
2012-11-01
599007 byte
Conference paper
Electronic Resource
English
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