For many reasons, the chip technology for spacecraft computing has lagged commercial systems by decades. Equally disconcerting, however, has been a similar lag in the computer architectures used. This paper will look at an emerging class of multi-core processor architectures, called “tiled,” extrapolate what they might look like in the future, and how they might be adapted to space applications. This extrapolation will include physical characteristics (speed, power, and area), system architectures, and fault tolerant models


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    Title :

    An Exploration of Tiled Architectures for Space Applications


    Contributors:


    Publication date :

    2009-07-01


    Size :

    390270 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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