Modern Field Programmable Gate Arrays (FPGAs) offer a solution to several issues related to real-time on-board systems, such as guaranteed execution time. They are currently considered as target platforms for space applications. How-ever, the complexity of producing circuits on these components poses a challenge to their widespread adoption. To address this issue, high-level synthesis tools provide another layer of abstraction above the logic circuit design process, for example compiling C code into Hardware Description Languages such as VHDL or Verilog. However, high-level synthesis results are poorly predictable and do not guarantee the efficient use of recent FPGA capabilities provided by new primitives like digital signal processor or random-access memory. In this paper we propose a compilation chain dedicated to reactive systems, ie. controllers, providing a more predictable synthesis process for critical embedded control applications. The implemented solution demonstrates timing performance equivalent to the traditional synthesis process with a more predictable result.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    A Reactive System-Specific Compilation Chain from Synchronous Dataflow Models to FPGA Netlist


    Contributors:


    Publication date :

    2024-07-15


    Size :

    590689 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    Scheduled Dataflow Architecture: A Synchronous Execution Paradigm for Dataflow

    Kavi, K. M. / Kim, H.-S. / Hurson, A. R. | British Library Online Contents | 1999


    Tabu Search: Implementation & Complexity Analysis for Netlist Partitioning

    Areibi, S. / Vannelli, A. | British Library Online Contents | 2003


    Component-Level Dataflow Analysis

    Rountev, A. | British Library Conference Proceedings | 2005


    The Mosaic CGNS Dataflow Platform

    Poinot, Marc / Brunet, Vincent / Costini, Pierre et al. | AIAA | 2019


    SCHEDULE COMPILATION SYSTEM

    SEKINO TOKITAKA / KITAGAWA YUKIHIKO / SHIMOMURA AKIRA | European Patent Office | 2015

    Free access