For low-power, high-performance circuits, dual edge triggered (DET) synchronized operation is highly attractive. When paired with half the clock frequency, DET operation can achieve the same throughput as traditional single-edge synchronous systems. On the clock network, which frequently contributes significantly to the total power usage of the system, this may result in significant power savings. However, specific registers that sample information on both clock edges must be created to be able to accomplish DET FF operation. Compared to their single-edge equivalents, these registers are more complicated and frequently have some clock overlay between the internal inverted clock and the main clock. This study introduces a revolutionary static DET flip flop (DET FF) that does not require a clock edge that is inverted for functionality, thus totally avoiding clock overlap concerns with a true single phased clock (TSPC). The suggested concept employs a single transistor-clocked (STC) buffer along with auto-gated clock gating technique to overcome redundant transition power with less dynamic power consumption than the current a few state-of-the-art designs. Cadence Virtuoso Design suite with 45nm CMOS technology is used to simulate the design. The suggested design outperforms the current designs with respect to power (14%), and power-delay-product, or PDP (11%) for a 10% switching activity.
TSPC STC-DET Flip-Flop With Autogated Clock Gating For Low-Power
2024-11-06
682549 byte
Conference paper
Electronic Resource
English
NTRS | 1984
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