To decrease a number of fail safe computers while suppressing an increase of wiring between housings.SOLUTION: CPUs (failsafe computers) are removed from many ATC/TD transmitters 61 accommodated in a transmitter housing 14, programs 33-36 in the CPU are transferred to a CPU66 (failsafe computer) of a small number of logic parts 83 accommodated in a logic part housing 12 and thus not only numbers of CPU and unit are decreased but also transferring measuring circuits 86, 85, 56 to the logic parts 83 makes wiring between housings 71-73 limited. Also, collecting plural measuring circuit sets 86, 85, 56 in a single unit, utilizing facilitated bus line connections (67) by integrating CPUs brings about a decreased unit number and also the measurement of frequencies equivalent to the measuring object of frequency measuring circuits 85, 86 from transmission waves C of the measuring object of a level measuring circuit 56 further makes wiring 73 between housings limited.SELECTED DRAWING: Figure 3
【課題】筐体間配線の増加を抑制しつつフェールセーフコンピュータの個数を減らす。【解決手段】送信部筐体14に収容される多数のATC/TD送信器61からCPU(フェールセーフコンピュータ)を無くし、それに搭載されていたプログラム33〜36を論理部筐体12に収容される少数の論理部83のCPU66(フェールセーフコンピュータ)に搭載してCPUやユニットの個数を減らすとともに、測定回路86,85,56を論理部83に移設して筐体間配線71〜73を限定する。また、CPUの統合によるバスライン接続(67)の容易化を利用して複数組の測定回路86,85,56を一ユニットに纏めることでユニットの個数を更に減らすとともに、レベル測定回路56の測定対象の送信波Cから周波数測定回路85,86の測定対象相当の周波数を計測することで筐体間配線73の本数限定を更に進める。【選択図】 図3
TRACK CIRCUIT TRANSMITTER
軌道回路用送信装置
2019-09-05
Patent
Electronic Resource
Japanese
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