Compact two-step parallel modified-signed-digit adder/substractor based on binary logic operations using electron-trapping devices [3805-05]
Meeting, Photonic devices and algorithms for computing ; 1999 ; Denver; CO
1999-01-01
10 pages
Conference paper
English
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Quaternary signed-digit arithmetic operations for optical computing [3805-28]
British Library Conference Proceedings | 1999
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IEEE | 1994
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