Several conditions can cause a microprocessor to go into a reset state. The real-time control systems commonly found in automobiles or machinery must manage reset conditions well to prevent the system from damaging the mechanisms being controlled or from causing other disastrous consequences. One way to manage such difficulties is to construct a state machine that prioritizes and handles each reset. The state machine detects common reset conditions, such as loss of clock or improper address accesses, signals the processor reset line, and generates the address of the routine that handles the exception. This address is put on the address bus for use by the CPU. In one case, such a state machine was implemented on the same IC as an enhanced 6800-type processor for use in automotive engine control. The same logic states can be used to develop similar circuits for other applications. Such a state machine could be implemented either in discrete circuits or as a semicustom IC. In addition, some standard microprocessors will shortly provide reset-detection facilities on chip. The 68HC11 processor, for example, will contain loss-of-clock detection.
Prioritized resets for microprocessors
Vorrangige Loeschungen fuer Mikroprozessoren zur Vermeidung von Schaeden
Machine Design ; 57 , 11 ; 128-132
1985
Aufsatz (Zeitschrift)
Englisch
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