Using a gate-level emulation of a typical avionics miniprocessor, fault injection experiments were performed to (1) determine the time-to-detect a fault by comparison-monitoring, (2) forecast a program's ability to detect faults and (3) validate the fault detection coverage of a typical self-test program. To estimate time-to-detect, six programs ranging in complexity from 6 to 147 instructions, were emulated. Each program was executed repetively in the presence of a single stuck-at fault at a gate node or device pin. Detection was assumed to occur whenever the computed outputs differed from the corresponding outputs of the same program executed in a non-faulted processor. Histograms of faults detected versus number of repetitions to detection were tabulated. Using a simple model of fault detection, which was based on an analogy with the selection of balls in an urn, distributions of time-to-detect were computed and compared with those obtained empirically. A self-test program of 2,000 executable instructions was designed expressly for the study. The only requirement imposed on the design was that it should achieve 95 % coverage. The program was executed in the presence of a single stuck-at fault at a gate node in device pin. The proportion of detected faults was tabulated.
Methodology for measurement of fault latency in a digital avionic miniprocessor
Ein Verfahren zur Bestimmung der Fehlerlatenz in einem digitalen Bordrechner
1981
14 Seiten, 5 Bilder, 11 Tabellen, 5 Quellen
Aufsatz (Konferenz)
Englisch
Methodology for measurement of fault latency in a digital avionic miniprocessor
Tema Archiv | 1981
|Tema Archiv | 1977
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