A method of implementing high-speed IIR digital filter in FPGA is proposed, and the stability problem of IIR digital filter coefficients after rounding is theoretically analyzed; the filter is designed using FDATool, and the simulation is programmed in Matlab; the method of experimental simulation is used. Determine the quantization word length of the IIR filter coefficients to ensure the optimization of IIR filter performance and hardware resources, so that the IIR filter can be applied to high-speed occasions. The calculation characteristics of the calculation components in the FPGA are studied, and the Verilog hardware description language is used to implement iterative calculations and Symbol number multiplication; Finally, the IIR digital filter is programmed to be realized by simulation and implemented on FPGA. It is verified by experiments that the IIR digital filter designed by this method converges and can be applied to systems that require high real-time performance.


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    Titel :

    Design of IIR Digital Filter Based on FPGA


    Weitere Titelangaben:

    Lecture Notes on Data Engineering and Communications Technologies


    Beteiligte:
    J. Jansen, Bernard (Herausgeber:in) / Liang, Haibo (Herausgeber:in) / Ye, Jun (Herausgeber:in) / Wang, Chuang (Autor:in) / Xi, He (Autor:in) / Chen, Tienian (Autor:in) / Liu, Jiawei (Autor:in)


    Erscheinungsdatum :

    27.09.2021


    Format / Umfang :

    7 pages





    Medientyp :

    Aufsatz/Kapitel (Buch)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch





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