Abstract In this paper we present a method to estimate the scheduling discipline applied on the output port on an Ethernet switch. We use well known formulas to calculate the expected output rate of a scheduler. Assuming that it is one of the following scheduling algorithms FIFO, Fixed Priority or Round Robin, we measure the actual output bandwidth and find the most likely scheduling algorithm. We present both a simulation study and a practical implementation where the proposed principle is implemented on a FPGA based high-pression Ethernet testbed.


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    Titel :

    Estimating the Scheduling Discipline of an Ethernet Switch Using Constant Bit-Rate Probes


    Beteiligte:


    Erscheinungsdatum :

    2013-01-01


    Format / Umfang :

    10 pages





    Medientyp :

    Aufsatz/Kapitel (Buch)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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