Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.


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    Titel :

    Estimating Delays In ASIC's


    Beteiligte:
    Burke, Gary (Autor:in) / Nesheiwat, Jeffrey (Autor:in) / Su, Ling (Autor:in)

    Erschienen in:

    Erscheinungsdatum :

    01.08.1994



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch




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