Proposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.
Fast, Massively Parallel Data Processors
NASA Tech Briefs ; 18 , 8
01.08.1994
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Keine Angabe
Englisch
Fast, Massively Parallel Data Processors
Online Contents | 1994
The Massively Parallel Processor
AIAA | 1982
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