Accurate, all-digital, high-speed processor comprising correlator and down-converter developed for receivers in Global Positioning System (GPS). Processor reduces roundoff and commensurability errors to extremely small values. Use of digital chip and phase advancers provides outstanding control and accuracy in phase and feedback. Great flexibility imparted by provision for arbitrary starting time and integration length. Minimum-bit design requires minimum number of logical elements, thereby reducing size, power, and cost.
Counterrotator And Correlator For GPS Receivers
NASA Tech Briefs ; 13 , 6
01.06.1989
Sonstige
Keine Angabe
Englisch
Improved Correlator Peak Selection for GNSS Receivers in Urban Canyons
Online Contents | 2015
|British Library Conference Proceedings | 2006
|The Effect of Correlator and Front-End Design on GNSS Pseudorange Biases for Geodetic Receivers
Online Contents | 2016
|The effect of correlator and front‐end design on gnss pseudorange biases for geodetic receivers
British Library Online Contents | 2016
|