Circuit is self-biasing, with differential current-to-voltage conversion. CMOS current-differencing readout consists of dc-balanced pair of virtual ground stages and current-differencing circuit similar to circuit mirror. Triode multiplier cell replaces test sources to form monolithic configuration. Transistors belonging to selected multiplier cell need to be duplicated for each multiplier within correlator chip. Remaining elements form part of readout and may be scaled as single common readout stage.


    Zugriff

    Zugriff über TIB

    Verfügbarkeit in meiner Bibliothek prüfen


    Exportieren, teilen und zitieren



    Titel :

    Monolithic CCD-array readout


    Beteiligte:
    Farnsworth, D. L. (Autor:in) / Lampe, D. R. (Autor:in) / Shutt, T. J. (Autor:in)

    Erschienen in:

    Erscheinungsdatum :

    1981-01-01



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch


    Schlagwörter :


    Correlated readout: a new readout method of focal plane array [3360-07]

    Qiu, C. / Wang, X. / Chin, K. K. et al. | British Library Conference Proceedings | 1998


    A monolithic myP-ready sum of delta readout circuit with integrated capacitive sensors

    Steger, M. / Nebel, G. / Sauerbrey, J. et al. | Tema Archiv | 1996


    Fabricating Microbolometer Array on Unplanar Readout Integrated Circuit

    Wang, H. / Yi, X. / Lai, J. et al. | British Library Online Contents | 2005


    Cryogenic Readout Amplifiers for FIRST's Stressed Ge:Ga Array

    Dierickx, B. / Seijnaeve, J. / Scheffer, D. | British Library Online Contents | 1996


    Optical Link For Readout From Focal-Plane Array

    Fossum, Eric R. / Larsson, Anders G. / Maserjian, Joseph | NTRS | 1992