A familiar two-transistor saturable-core parallel inverter is modeled as a nonlinear negative resistance in parallel with energy-storage elements. The techniques of singular-point analysis are combined with piecewise linear techniques to permit determination of solution trajectories on the phase plane. Clear insight is provided, not only into steady-state oscillation, but also into transient behavior of the circuit. Experimental results confirming the analytical model are included.
Analysis of Limit Cycles in a Two-Transistor Saturable-Core Parallel Inverter
IEEE Transactions on Aerospace and Electronic Systems ; AES-9 , 4 ; 571-584
01.07.1973
4403963 byte
Aufsatz (Zeitschrift)
Elektronische Ressource
Englisch
Unsaturating Saturable Core Transformer
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