The maximum likelihood (ML) phase error detector (PED) for 16-APSK is derived and analyzed. The ML PED is used as part of a phase lock loop (PLL) to perform carrier phase synchronization and, to a limited extent, frequency offset synchronization. Compared to other PEDs suitable for use with 16-APSK, the results show that a PLL using the ML PED achieves lower estimator error variance than a PLL using the other PEDs at low signal-to-noise ratios. As the signal-to-noise ratio increases, the performance of the PLL based on all the PEDs are the same.


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    Titel :

    On the Maximum Likelihood Non-Data-Aided Phase Error Detector for 16-APSK


    Beteiligte:
    Rice, Michael (Autor:in) / Redd, Bryan (Autor:in) / Twitchell, Autumn (Autor:in)


    Erscheinungsdatum :

    2022-03-05


    Format / Umfang :

    2929073 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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