In this paper, we propose a novel high speed VLSI architecture of full search-variable block size motion estimator (VBSME) supporting multiple referenceframes. In the proposed architecture, four current macrobocks are concurrently compared with a single search window (SW) of the reference frame to find the best matched block. By reusing the SW of the referenceframe and scheduling the architecture in pipeline, the proposed architecture can reduce the memory bandwidth and the execution time. Then, 71.73% of local memory size and 69.34% of system memory bandwidth were saved compared with non pipelined-MRFME (NP-MRFME). Under a operating frequency of 162.43MHz, the architecture can support the real-time processing of 1280x720 picture size at 30fps. The architecture has been prototyped in Verilog HDL and synthesized by Synopsys Design Compiler with Samsung 0.18um standard cell library.
A High Speed VLSI Architecture of Full Search Variable Block Size Motion Estimator for Multiple Reference Frames
2008 Congress on Image and Signal Processing ; 1 ; 119-123
01.05.2008
425497 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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