A methodology for designing radiation tolerant CMOS APS SOC image sensors is presented. It is based on the experimental results of test chips that had been designed, fabricated, and characterized. Details of the basic building blocks of a proposed design are presented. The proposed design is in a 0.35-/spl mu/m CMOS standard process. The radiation tolerance level could be up to 30 Mrad (Si) total dose of ionizing radiation. The proposed methodology has the potential of yielding highly integrated, highly functional, highly compact, low power, radiation tolerant, cost effective CMOS APS SOC image sensors.
Design of radiation tolerant CMOS APS system-on-a-chip image sensors
01.01.2002
1112557 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
7.0402 Design of Radiation Tolerant CMOS APS System-on-a-Chip Image Sensors
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