Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation is becoming more complex, difficult, and costly. Furthermore, circuit designs are increasingly being developed through the use of powerful VLSI computer-aided design (CAD) synthesis tools which emphasize circuit descriptions using high-level representations of functional behavior, rather than physical architectures and layout. Behavior fault simulation applied to the top functional level models described using a hardware description language offers a very attractive alternative to these problems. A new way to simulate the behavioral fault models using the hardware description language (HDL), such as VHDL, is presented. Tests were generated by carrying out the behavioral fault simulation for a few circuit models. For comparison, a gate-level fault simulation on the equivalent circuit, produced via a synthesis tool, was used. The performance analysis shows that a very small number of test patterns generated by the behavioral automatic test pattern generation (ATPG)/fault simulation system detected around 98 percent of the testable gate-level faults that were detected by random test.


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    Titel :

    VHDL behavioral ATPG and fault simulation of digital systems


    Beteiligte:
    Chen, C.-I.H. (Autor:in) / Noh, T.H. (Autor:in)


    Erscheinungsdatum :

    1998-04-01


    Format / Umfang :

    1873302 byte




    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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