A high-performance low-power radar signal processor is being developed for the Discoverer II space-based radar application. The signal processor will perform real-time ground moving target indication (GMTI) and synthetic aperture radar (SAR) front-end signal processing functions, which significantly reduces the downlink communication bandwidth. In order to minimize the signal dispersion, the wideband receive signal is first channelized into multiple digital subbands and all the subsequent processing tasks including beamforming, pulse compression, and space-time adaptive processing (STAP) are done in the subband domain. In order to meet over one trillion operations per second (Teraops) computational throughput requirement with low power consumption and small form factor, a highly optimized scalable VLSI bit-level systolic array technology is used. The 1 Teraops on-board processor is currently projected to consume less than 50 watts and to be less than 1/8 cubic foot and 12 kg.


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    Titel :

    One trillion operations per second on-board VLSI signal processor for Discoverer II space based radar


    Beteiligte:
    Song, W.S. (Autor:in) / Baranoski, E.J. (Autor:in) / Martinez, D.R. (Autor:in)


    Erscheinungsdatum :

    01.01.2000


    Format / Umfang :

    615931 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    One Trillion Operations per Second On-Board VLSI Signal Processor for Discover II Space Based Radar

    Song, W. S. / Baranoki, E. J. / Martinez, D. R. et al. | British Library Conference Proceedings | 2000


    Precision radar surveillance and mapping with Discoverer II

    Koss, John / Trichel, Milton / Pohlig, Stephen et al. | AIAA | 1999


    Design of a Space-based Radar Signal Processor

    Nohara, T.J. | Online Contents | 1998