The adoption of multi-core processors in airborne safety-critical systems has been troublesome to the aeronautic industry. This type of processor inserts new sources of non-determinism on application execution, increasing difficulty to perform safety analysis that relies on Worst-Case Execution Time (WCET). Design recommendations to mitigate non-determinism in airborne multi-core systems are presented in this work. A prototype of platform was constructed in order to demonstrate feasibility of non-determinism mitigation recommendations. We utilized the prototype to experiment with parallel memory access. The recommendations are a sound basis to allow multi-core processors to be used in airborne systems, however, some changes are required.


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    Titel :

    Design recommendations to mitigate memory and cache non-determinisms in multi-core based IMA platform of airborne systems




    Erscheinungsdatum :

    01.09.2015


    Format / Umfang :

    765541 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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