VLSI fabrication (VLSI Fab) process is perhaps one of the world's most complex manufacturing process carried out under highly stringent parameters of man, machine & environment. Generally, a ‘Wafer Lot’ of 25 silicon wafers goes through about 500 steps in the process of fabrication. Each step can introduce ‘Defects' on wafers. SCL's (Semi-Conductor Laboratory, India) in-house developed Defect Database Management System (DDMS) is essentially a Wafer Inspection and Review Data Management Tool that takes defect data generated from VLSI Inspection Stations, convert it into standard data format and integrates it with Defect Images and Bit Maps. This integrated data is used for review, analysis, and evaluation of defects and to generate various reports which are useful for yield improvement. Defect Classification is a process of assigning class to defects and reviewing the defect class generated by tool. Defect class helps engineers to find out root cause of the occurrence of defects.


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    Titel :

    Defect Data Classification and Analysis in VLSI Fabrication


    Beteiligte:


    Erscheinungsdatum :

    01.03.2018


    Format / Umfang :

    2801270 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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