A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.


    Zugriff

    Download


    Exportieren, teilen und zitieren



    Titel :

    Input signal mismatch detection circuit


    Beteiligte:

    Erscheinungsdatum :

    09.05.2017


    Medientyp :

    Patent


    Format :

    Elektronische Ressource


    Sprache :

    Englisch


    Klassifikation :

    IPC:    B60R Fahrzeuge, Fahrzeugausstattung oder Fahrzeugteile, soweit nicht anderweitig vorgesehen , VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR / G06F ELECTRIC DIGITAL DATA PROCESSING , Elektrische digitale Datenverarbeitung / H03K PULSE TECHNIQUE , Impulstechnik



    INPUT SIGNAL MISMATCH DETECTION CIRCUIT

    KRISHNA SIDDHARTHA GOPAL / LYNCH RUSSELL J / VARMA VIKRAM | Europäisches Patentamt | 2016

    Freier Zugriff

    Circuit and method for reducing mismatch for combined clock signal

    SHI MINGFU | Europäisches Patentamt | 2018

    Freier Zugriff

    Input circuit for signal security device

    HUANG KEYONG / WANG WEIYI / MI YAN | Europäisches Patentamt | 2021

    Freier Zugriff

    INPUT SIGNAL ERRONEOUS DETERMINATION PREVENTION CIRCUIT

    XIE CHUAN | Europäisches Patentamt | 2018

    Freier Zugriff