A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.
Circuit and method for reducing mismatch for combined clock signal
25.12.2018
Patent
Elektronische Ressource
Englisch
IPC: | H04B TRANSMISSION , Übertragung / B60T Bremsanlagen für Fahrzeuge oder Teile davon , VEHICLE BRAKE CONTROL SYSTEMS OR PARTS THEREOF / G01R Messen elektrischer Größen , MEASURING ELECTRIC VARIABLES / G09G Anordnungen oder Schaltungen zur Steuerung oder Regelung von Anzeigevorrichtungen mit statischen Mitteln zur Darstellung veränderlicher Informationen , ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION / H03K PULSE TECHNIQUE , Impulstechnik / H03L Automatisches Steuern oder Regeln, Inbetriebsetzen, Synchronisieren oder Stabilisieren elektronischer Schwingungs- oder Impulserzeuger , AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES |
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