Rank Based Optimized Sorting Network Architecture for Hardware Implementation of ROF
International conference on visual information engineering; VIE 2006: visual information engineering innovation and creativity in visual media processing and graphics ; 2006 ; Bangalore, India
01.01.2006
5 pages
Includes bibliographical references and index
Aufsatz (Konferenz)
Englisch
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Novel optimized implementation of CABAC hardware encoder
British Library Online Contents | 2009
|Novel optoelectronic sorting network with recirculating architecture [3551-28]
British Library Conference Proceedings | 1998
|A Hardware FPGA Implementation of a 2-D Median Filter Using a Novel Rank Adjustment Technique
British Library Conference Proceedings | 1999
|