Verification of Solid State Interlocking Programs
Formal Implementation of Data Validation for Railway Safety-Related Systems with OVADO
Verification of Scheme Plans Using CSP||B
Applied Bounded Model Checking for Interlocking System Designs
Twenty-Five Years of Formal Methods and Railways: What Next?
Validation of Railway Interlocking Systems by Formal Verification, A Case Study
2011-01-1266 High Voltage Connect Feature
2011-01-1265 Virtualization for ECU Platform Software Testing in Automotive Embedded
2011-01-1044 ADACS: Advanced Diagnosis for Time-Triggered Automotive Communication Systems