The authors describe an integrated testing approach called the Maintenance and Diagnostic System (MADS), which was developed for digital avionics systems using VHSIC and semicustom devices. Mission/operational requirements dictate high availability with capability to detect 98% of all faults and isolate 90% of these faults to a line replacement module (LRM) or 95% of the faults to two LRMs. MADS achieves these goals by defining a module maintenance node (MMN) chip set for each LRM in the system and the design for testability concepts for hardware. The MMN aids parallel, high-speed testing of LRMs, isolating the fault(s) to a module/chip level while incurring less than 10% overhead. It uses the concepts of scan set design, pseudorandom test vector generation, output response compression, and separate scan set loops to test the SSI-MSI logic on the LRM. It also stores interim test results and run-time fault information to isolate the hard-to-reproduce failures and performs verification of interchip and intermodule wiring.


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    Title :

    Design for testability for future digital avionics systems


    Additional title:

    Pruefsystem-Entwurf zur Pruefung zukuenftiger Digital-Avioniksysteme


    Contributors:


    Publication date :

    1988


    Size :

    5 Seiten, 5 Quellen



    Type of media :

    Article (Journal)


    Type of material :

    Print


    Language :

    English




    Design for testability for future digital avionics systems

    Subramanyam, V.R. / Stine, L.R. | Tema Archive | 1986


    Design for testability for future digital avionics systems

    Subramanyam, V.R. / Stine, L.R. | IEEE | 1988


    Testability management for digital avionics

    Keiner, W.L. | Tema Archive | 1986


    Avionics hardware design for testability

    FERRELL, B. / OVER, S. | AIAA | 1984


    Testability Considerations in High-Performance Avionics Processors

    Loo, T. / IEEE / AIAA | British Library Conference Proceedings | 1992