In the paper the high-speed architecture of built-in self test (BIST) for double data rate synchronous dynamic random access memory (DDR SDRAM) is proposed. The BIST proposed can make self testing at its operating frequency that improves the reliability of the results obtained.


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    Title :

    The Architecture of DDR Memory Device Self Test Tools for Spacecraft Control Systems


    Additional title:

    Russ. Aeronaut.


    Contributors:

    Published in:

    Russian Aeronautics ; 64 , 2 ; 330-336


    Publication date :

    2021-04-01


    Size :

    7 pages




    Type of media :

    Article (Journal)


    Type of material :

    Electronic Resource


    Language :

    English




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