As technology reduces to nm range, switching power, short-circuit power, and total power consumption decrease, while leakage powerLeakage Power consumption increases. There have been a few techniques reported to reduce leakage powerLeakage Power consumption, but it remains unclear which technique is the most effective for power reductionReduction at the 16 nm technology node. The main aim of this paper is to determine the various elements of power consumption in complementary metal–oxide–semiconductor (CMOS) circuits at various technology nodes as well as to determine the most effective method of leakage reductionReduction at 16 nm technology. In this paper, various leakage reductionReduction techniques are compared using a spice simulationSimulation tool and a 16 nm predictive technology model (PTM) CMOS model. As a result, it has been concluded that the best method for reducing leakage is the sleep transistorSleep Transistor method among lectorLECTOR, ONOFICONOFIC, dual-stackDual-stack, and sleepy keeper transistor techniques. Compared with a sleep transistorSleep Transistor technique, lectorLECTOR, ONOFICONOFIC, dual-stackDual-stack, and sleepy keeper techniquesSleepy Keeper Techniques exhibited 151×, 156×, 2.91×, and 1.2 × times higher leakage powerLeakage Power consumption, respectively. This study may contribute to the finding of an effective leakage reductionReduction technique appropriate for CMOS circuit scale technology nodes.
Leakage Power Reduction in CMOS Inverter at 16 nm Technology
Lect. Notes Electrical Eng.
International Conference on Robotics, Control, Automation and Artificial Intelligence ; 2022 November 24, 2022 - November 26, 2022
2023-11-18
13 pages
Article/Chapter (Book)
Electronic Resource
English
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