The use of COTS FPGAs as deployment platform of microprocessor based systems represents an attractive alternative on aerospace applications, because their programmability, performance and cost-effectiveness. However, traditional hardening has a remarkable impact on resources and performance that limits their applicability. Selective hardening, that is protecting only the design’s most error-sensitive parts, reduces significantly overheads keeping a reasonable reliability at the same time. This chapter describes and illustrates, with experimental results, this method and presents a hybrid strategy, called co-hardening, to leverage the benefits of adopting selective hardening on both hardware and software.
Reducing Implicit Overheads of Soft Error Mitigation Techniques Using Selective Hardening
FPGAs and Parallel Architectures for Aerospace Applications ; Chapter : 17 ; 259-278
2016-01-01
20 pages
Article/Chapter (Book)
Electronic Resource
English
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